Integrated circuits have permeated into every aspect of modern society. They are the building blocks used to create everything from the information super-highway to the electronic timer in the family toaster. Generally, any device that is used today that is considered “electronic” utilizes one or more integrated circuits. These often-unseen entities help to reduce the daily workload, increase the safety of our air traffic control systems, and even let us know when it is time to add softener to the washing machine. Modern society has come to rely on these devices in almost every product produced today. And, as we progress further into a technologically dependent society, the demand for increased device speeds, capacity and functionality drive integrated manufacturers to push the edge of technology even further.
In the integrated circuit industry, there is a continuing trend toward higher device densities. To achieve these high device densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels) on semiconductor wafers. In order to accomplish such densities, smaller feature sizes and more precise feature shapes are required. This may include width and spacing of interconnecting lines, spacing and diameter of contact holes, and surface geometry, such as corners and edges, of various features. The dimensions of and between such small features can be referred to as critical dimensions (CDs). Reducing CDs and reproducing more accurate CDs facilitates achieving higher device densities.
Currently, optical microlithography is a technology employed to pattern integrated circuit designs onto a silicon wafer. Success of microlithography can be attributed to ease of transferring layout patterns to silicon by optical projection printing, high yield, and high throughput. As CDs continue to shrink, however, image quality related to microlithography can erode, as design patterns are shrinking at a faster rate than technology related to smaller light wavelengths is advancing. Optical proximity correction (OPC) is one particular system/methodology that can be employed to increase resolution of a microlithography process and/or compensate for known pattern non-idealities.
Specifically, OPC is a mask-engineering technique that is employed to facilitate patterning on a silicon wafer in manner that matches a design for that pattern. OPC is employed to compensate mask geometry for known effects that occur during imaging or subsequent processing. Typically, an integrated circuit design is generated that is desirably patterned onto a wafer. The design is placed onto a mask (reticle), and thereafter patterned onto silicon. The design patterned on the mask, however, often does not translate well to the wafer, especially in light of continued decreases in CDs.
OPC is associated with various benefits in connection with manufacturing integrated circuits. For example, OPC can enhance process window(s), thereby providing a higher yield. Further, utilizing OPC can result in better circuit performance for a given minimum feature size, due to line-width uniformity that allows for faster clock rates. Moreover, smaller design rules can be adopted, enabling further shrinking of CDs. While OPC provides these and other benefits to integrated circuit manufacturing, it is a time consuming process and can require a substantial amount of computing resources to generate accurate simulations of mask adjustments. This is because conventional OPC requires movement of particular line edges on a mask to optimize printability, which consequently disturbs interconnected line edges and/or adjacent line edges. For instance, edges on a mask are required to be broken and moved, resulting in interaction among various other edges. Due to such movements, a final OPC correction may not be optimal.
There are various factors that can contribute to a need for OPC, as all steps utilized in integrated circuit manufacturing can cause errors during pattern transfer of the original layout design to silicon. For example, physical errors in the mask can be generated during mask manufacturing, causing the printed mask to be disparate from the ideal design. Also, as designs continue to shrink, the lithography process without OPC can result in a pattern upon the silicon that is not desirable. Resist development and etching can also be associated with errors that result in lessening fidelity between an idealized pattern and a resultant pattern upon silicon. These and other processes can cause corner rounding and lack of CD accuracy upon a pattern.
Historically, an engineer completed OPC manually (e.g., the engineer would alter line edges manually utilizing trial and error to obtain an acceptable pattern upon a wafer resulted). As CDs continue to shrink, manual OPC has become less effective. For instance, each time an edge is moved, other edges are affected. As spaces between edges decrease, this manual procedure will become nearly impossible. Thus, automation techniques have been recently developed to make up for these deficiencies. Particularly, rule based techniques and model-based techniques have been employed to automate OPC. Rule based techniques are an extension of methods utilized for manual OPC (e.g., through experimentation, corrections for a particular pattern layout are discovered). Rule based techniques are computationally fast, and can thus be applied to an entire integrated circuit layout. Model-based techniques utilize simulated models to compute wafer results and modify edges on the mask to improve such simulated results. The model-based techniques are capable of more general correction, but can require substantial amounts of time and computational resources. Accordingly, there exists a need in the art for an OPC system and/or methodology that provides optimal results in connection with pattern transfer while not requiring a substantial amount of time/computational resources.